The CDBC are quad cross-couple 3-STATE CMOS. NOR latches, and the CDBC are quad cross-couple STATE CMOS NAND latches. Each latch. Data sheet acquired from Harris Semiconductor. SCHSC – Revised March The CDB and CDB types are supplied in lead hermetic. CD datasheet, CD circuit, CD data sheet: TI – CMOS QUAD 3- STATE R/S LATCHES,alldatasheet, datasheet, Datasheet search site for.
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On processors such as the Atmel AVR that power is in the single microamp region – the clock doesn’t need to be running.
I would probably need to contemplate it for quite some time to fully grasp it. I had a sync. Can’t yet wrap my head around applying a D or JK that way. A state change on the inputs would wake the MCU – whereupon it reads the inputs and then goes back to sleep. The most complex part by design is planned to be the MCU. Look for “Wake-up on pin change”, not interrupt.
Never say fd4044 are nobody! Is datashert a reason why you have to use the fewest ICs? Home Questions Tags Users Unanswered.
The shortcoming is that I have 4 separate resets, while ideally I would need only one. Email Required, but never shown. You will then need pull-ups on every output instead of pull-downs, so just use the pull-ups of the MCU inputs by configuring it accordingly.
CD Datasheet Texas Instruments pdf data sheet FREE from
In this scenario a common reset channel on the IC would help maximizing the numbers of available latches in the same footprint and make the circuit more elegant and simple. Most MCUs inputs can’t be configured with internal pull-downs, only with pull-ups. But you all know how it works Any way, take into account that the SNN has been obsolete for 25 years, its not a good idea to even consider that part for a new design. Comments like these are one of the many reasons for which I regret skipping all the theory in the electronic classes and being in the first line only when there was the risk to toast stuff.
On top of that, when I will get into power-optimization for the MCU I may end up having to choose between keeping the interrupts alive or saving power. Their later comment says the MCU would be sleeping, before you posted your ‘answer’.
(PDF) CD4044 Datasheet download
Post as a guest Name. I would disagree, but I may be missing the picture here. I want to keep it flexible, both capability and power-usage wise and this requires balance.
You can derive a similar deduction for CD Following up my previous comment: The CD is indeed the one I have in the design now. Hi, thanks for the reply!
There’s a good chance that quiescent current added to the system by an extra logic IC would be greater than the current consumed by the MCU waking xd4044 and executing a handful of instructions. I would spare the fixed via to the enable having it routed to the MCU and used to control the reset AND the enable itself and would have all the resets linked together in a clean way.
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Is the enable line capable of effectively “resetting” the latches? Sign up or datasneet in Sign up using Google. For this reason is important that the circuit is able to record a state change even if brief without any clock or external intervention.
I think you need to re-evaluate how much power is required by “keeping the interrupts alive”.
As has been said, you can make this function from more 74HCT-etc gates. Historical anecdotes on my other uses for RS latches.